In a computer system with a plurality of devices interconnected by a communications channel, such as a bus, the overall achievable system speed is determined by the clock period of the communications channel. With reference to FIG. 1(a), device 100 and device 102 are interconnected by channel 110. Device 100 communicates with device 102 by sending output signal Q1 through channel 110 where it is received as data signal D2 by device 102.
The total time budget, T, for the channel clock period is described by the following equation: T=T.sub.CTO +T.sub.Z +T.sub.SU +T.sub.SKEW, where T.sub.CTO is the input clock to output phase delay of the source device; T.sub.SU is the set up time requirement of the destination device; T.sub.SKEW is the input clock skew between devices; and T.sub.Z is the transmission settling time of the communication channel.
T.sub.CTO, the input clock to output phase delay of a source device, is the amount of time taken between the beginning of a clock cycle as determined by clock input signal CLK and when output data signal Q1 is first available at an output port of the source device.
There are several factors responsible for the output phase delay of a device including the time required for the input clock signal to reach an output buffer of the device, the time required to pass a signal through the output buffer, and the delay introduced by a capacitive load on the output port of the device, driven by the output buffer. These factors are difficult to precisely predict because they vary significantly with process, temperature, and supply voltage differences. As a result, T.sub.CTO is determined by a tolerance for the maximum acceptable input to output phase delay under a variety of possible operating environments.
T.sub.Z, the transmission settling time of the communications channel, is the amount of time between a change in data signal Q1 and the corresponding change in D2. T.sub.SU, the setup time requirement of the destination device, is how long D2 must be valid before device 102 can read signal D2 at clock signal CLK'. Finally, T.sub.SKEW is the input clock skew between devices due to the inherent delay in delivering a clock signal to a plurality of devices. In FIG. 1(a), a clock signal is supplied to device 100 as signal CLK and to device 102 as signal CLK'. As illustrated in FIG. 1 (b), each of these delays contributes to the total clock period, T, as T.sub.CTO +T.sub.Z +T.sub.SU +T.sub.SKEW.
For a communications channel such as a PC bus, the output phase delay contribution, T.sub.CTO, accounts for much of the total time budget for the bus. For example, a typical bus timing specification for a 66 MHz bus allocates 7 ns for T.sub.CTO or nearly 50% of the 15 ns time budget. A 15 ns clock period for a 32-bit bus has a peak data bandwidth of 267 megabytes per second (MB/s). If the maximum T.sub.CTO amount can be reduced to 4 ns, then the clock period for the bus can be reduced to only 12 ns. The data bandwidth for 12 ns bus is about 333 MB/s for an improvement of about 25%. If the maximum output phase delay of a source device can be further reduced to 2 ns, then the resulting data bandwidth is about 400 Mb/s, an improvement of about 50% over specification.
Therefore, it is desirable to tighten the tolerance for the amount of output delay of a semiconductor device.